Field programmable logic devices (FPGAs) are a well-known type of digital integrated circuit that may be programmed by a user to perform specified logic functions. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The collective states of the individual memory cells then determine the function of the FPGA.
The configuration data may be read from memory (e.g., an external programmable read-only memory, or PROM) or written into the FPGA by an external device. Some FPGAs also support configuration via boundary scan or JTAG (Joint Test Action Group). IEEE Standard 1149.1 defines a four pin serial interface that drives a 16-state controller (state machine) formed in each compliant IC device. The four pins control transitions of the state machine and facilitate loading of instructions and data into the compliant IC device to accomplish pre-defined tasks. Originally, IEEE Standard 1149.1 was developed to perform boundary scan test procedures wherein the interconnections and IC device placement on printed circuit boards (PCBs) are tested through the connection pins of the PCBs (i.e., without the need for a mechanical probe). Since its establishment, some implementations of boundary scan have been extended to include additional test procedures such as device functional tests, self-tests, and diagnostics. More recently, boundary scan has been modified to provide In-System Programming, whereby configuration data is transmitted into a target programmable device after the device is mounted onto a PCB.
One FPGA supporting IEEE Standard 1149.1 is the XC4000.TM. FPGA from Xilinx, Inc. Boundary scan configuration of the XC4000 FPGA is described in detail in pages 8-45 through 8-52 of the Xilinx 1994 Data Book entitled "The Programmable Logic Data Book 1994" (hereinafter referred to as "the Xilinx 1994 Data Book"), published in 1994 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
When JTAG configuration is used, the FPGA is typically programmed by tester software as part of a sequence of test programs. In other words, the FPGA is programmed via JTAG, a test sequence is performed, and the FPGA is reprogrammed with another configuration in preparation for the next test sequence. Both configuration and test are performed by the same tester software, and the circuit board connections need not be changed back and forth between configuration mode and test mode during the testing process. Therefore, the ability to configure through JTAG considerably facilitates the testing process.
However, when the device is placed in user operation, the FPGA is typically configured using standard configuration methods, such as by reading a bitstream from a PROM. Various well-known configuration methods for the XC4000 FPGA are described in pages 2-32 through 2-45 of the Xilinx 1994 Data Book, which are incorporated herein by reference.
Since testing is performed through JTAG configuration, and user operation configures the device using other methods such as an external PROM, two separate sets of package pins are required to support the two types of configuration. Further, two separate sets of pads must be included on the FPGA in order to accommodate both test and user configuration. It is desirable to provide a method for configuring an FPGA for both test and user operation using the same set of pins, thereby reducing both packaging costs and FPGA manufacturing costs.